Willamette in-depth

Clock speeds

Historically, Intel has had a history of demonstrating processors at higher clock speeds than those available at launch. Couple this with Pentium III's being available at clock speeds up to 1GHz and it's probably safe to assume that Willamette will launch at a minimum of 1.0 or 1.1GHz with additional processors available at 1.2GHz, 1.3GHz, and (at most) 1.4GHz.

The main determinants of initial clock speed will most likely be yields as well as demand. Obviously the demand will be there if Willamette is priced affordably but if Willamette is priced like previous next-generation processors were on launch Willamette will likely be beyond the budget of most gamers.

Willamette Architecture Presentation

After the keynote address IDF split into various developer sessions, known as "tracks." For obvious reasons the IA-32 track was one of the more crowded sessions, as Intel's Glenn Hinton was going to discuss the details of the Willamette architecture.

Besides Willamette's clock speed Albert Yu dropped a few other buzzwords during the keynote: "400 MHz system bus", "SIMD-2", "hyperpipelined", and "arithmetic logic units running at twice the clock speed." However he didn't disclose the technical details of Willamette's architecture, that task was left to Glenn Hinton, an Intel engineer for the past 17 years.

According to Hinton, one of the main goals for Willamette was to "extend the basic features found in the P6 core." This means Intel wanted to create a processor with very deep speculative execution. If you recall, the Pentium Pro was Intel's first processor to support speculative execution. With it, the processor can continue to process instructions before it knows the results of others.

In particular, Willamette is capable of handling over "100 instructions in flight." This means exactly as it sounds, Willamette is capable of operating over 100 instructions at once.

By comparison, Athlon is capable of performing 72 operations at a time.

One of the key design goals Intel engineers wanted to achieve with Willamette was to reduce the gates per clock. This results in very little work done within a single clock cycle making each cycle extremely short. With a short clock cycle, the number of stages in Willamette was set at 20, giving it 8 more stages than Pentium III and 10 more than Athlon.

With such a long pipeline, Willamette requires more speculative techniques than previous P6 processors.