More VIA/HyperTransport

SuperSavage

Besides P4X266, VIA was also demonstrating its SuperSavage graphics core at Platform Conference. The follow-up to its Savage MX/IX range of graphics chipsets, SuperSavage offers additional performance with little power consumption - less than two watts of power.

The SuperSavage core

While VIA was demonstrating SuperSavage as a discrete graphics solution, VIA is aiming it squarely at the mobile market - an area where their Savage IX/MX graphics chips captured 20% of the market.

In terms of performance, SuperSavage will fall slightly behind GeForce2 Go, but with much better power consumption. In fact, VIA was demonstrating SuperSavage with Quake 3 running looped timedemos at a pretty good framerate for a laptop system. In terms of features, SuperSavage supports dual CRTs (ala DualHead, TwinView) via its DuoView+ technology, hardware motion compensation for DVD playback, and up to 64MB DDR SDRAM or SDR SDRAM all in one-chip. A second chip is needed for output to a DVI display.

In fact, VIA has already secured design wins from two top-tier notebook manufacturers for SuperSavage, although officials couldn't be specific on which OEMs were onboard. A little further down the road VIA plans to unveil its successor to SuperSavage dubbed UltraSavage although the final specs for this part have not been announced.

HyperTransport Consortium

AMD and its partners officially unveiled the HyperTransport Technology Consortium during Platform Conference. The consortium is a non-profit corporation created to promote and develop HyperTransport technology and any future specifications that may be needed in the future. The consortium is controlled by its members, which consist of AMD, API NetWorks, Apple Computer, Cisco Systems, NVIDIA, PMC Sierra, and Sun Microsystems, which also make up the executive committee of the consortium. Future companies can also sign on with one of two membership levels: contributors or adopters.

As you may know, HyperTransport is a point-to-point link for connecting circuits to each other. It can be used to connect chips inside PCs, or in networking and communications devices. Currently, clock speeds of 200, 400, 500, 566MHz and 800MHz are available with two bits of data transferred per clock cycle for an effective transfer rate of 1600MB/sec. Pair an 800MHz HyperTransport device up with a 32-bit wide bus, and you've got a peak bandwidth figure of 12.8GB/sec.

With so much bandwidth on tap and its natural flexibility, it will be interesting to see how HyperTransport evolves. Now that the charter members have gotten together and formed the consortium the specification is poised to move forward, and as you can see it consists of a wide variety of companies. Unlike Intel's 3GIO technology, HyperTransport is here now and running in products from API NetWorks (the AP1011 HyperTransport-to-PCI bridge which was actually offering 2GB/sec bandwidth between two systems on the show floor) and NVIDIA (nForce), with future products to come. It will be interesting to see if AMD and its partners are able to get HyperTransport in the mainstream or if it will serve its purpose in the interim until 3GIO takes off in a few years.