The RAMBUS Specification

Skinny and Fast: A Geek's Dream?

The Rambus architecture pushed by Intel is based on the idea that a simple memory interface can run at a much faster speed. This is a page from the RISC playbook: sacrifice functionality per clock cycle to reduce complexity, and crank up the MHz instead. In theory, this practice should work wonders. The PC Rambus specification calls for a serial 16-bit bus running at 400Mhz, and transferring data on both the up and down cycles of the clock, giving it an effective speed of 800Mhz. The theoretical bandwidth of this connection can be easily calculated: 16bits/transfer x 2transfers/cycle x 400Mcycles/second x 1bit/8bytes = 1.6GBytes/sec. Rambus has twice the bandwidth of PC100 SDRAM. Unfortunately, current processors cannot access memory this quickly, but when combined with DMA access from non-CPU peripherals, a good chunk of this bandwidth will soon be necessary.

Rambus Design

You may be asking yourself, 400Mhz, isn't that pretty fast for a memory system? Yes, it is, that's why Intel shrunk the data path to 16bits. Rambus uses only 30 matched copper lines between the memory controller and the memory modules (called RIMMs). By reducing the length and number of these lines, Rambus has reduced the amount of electromagnetic interference during data transfers, and more importantly, the capacitance of the interconnects, a prime stumbling block to high clock speeds.

If the design's so great, what's wrong with it?

Unfortunately, there is another problem that travels with high clock speeds: heat. RIMMs are the first memory modules equipped with heat sinks, and the Rambus specification calls for the memory subsystem to have its own cooling fan! Even these precautions are not enough to prevent your memory from melting, so Rambus has had to make a compromise between speed and heat management.

Update:
According to Rambus, the RDRAM specification never called for its own cooling fan.

Rambus modules have four power modes: active, standby, nap, and powered down. During a transfer, a module is in active mode, and is running at a full 2.2v, after the requested data is transferred, the individual module switches into standby, during which it receives only the power necessary to keep its data and be able to respond to requests. The next time a request comes in, the module has to power itself up to active again, a process that requires up to 100ns! That's 40 wasted time steps during which no data can be transferred. A quick calculation reveals that if every transfer required 100ns, the bandwidth would drop to 100MB/s, a 16th of the expected rate.

Rambus Power Modes

More Rambus Trouble

Rambus has been facing problems on the manufacturing front as well. Memory companies have found themselves in the unenviable position of being pulled four ways at once; many of them are trying to produce good ol' PC66, PC100, PC133 and RDRAM chips at the same time. This means different production lines for chips and PCBs for each of these memory types.

While Intel has poured a good deal of investment money into upgrading Korean and Taiwanese fabs, the yield of 400MHz chips has been abysmal. In an effort to keep the appearance of a schedule, Intel and Rambus introduced two watered down versions of Rambus, one running at 300Mhz, RD600, and one at 350Mhz, RD700. Motherboards with RDRAM ability are just now becoming available, although actual RIMMs are extremely rare and expensive.