Main Memory

Memory Arrangement

Memory is arranged by bit density in values of columns and rows. Each bit cell is given a unique binary address so that the system can keep track of what data is where. Using the Intel 2147H SRAM chip as an example, this chip can store 4096X1bits, which means that it can store 4096 memory locations, with each location containing one bit of information. Internally the chip is arranged in an array of 64 columns and 64 rows.

Using some basic math, we see that 64X64=4096, which is the total storage capacity of the SRAM. Since we know that 8 bits equals one Byte, we can determine that 4096/8 (read as 4096 divided by 8) gives us 512KB, so this chip can store 512KB of information. This equates into 128 4KB memory pages, however memory pages may be handled in different sizes by different operating systems.

Multiple Chip configurations

What if you need more storage capacity than one chip is capable of supplying? This is certainly a possibility, so to increase storage capacity you can link separate chips together to create a memory bank. If you 1MB of storage, this can be attained using two 2147H SRAM and linking the two together to create a memory bank of 4096X2, giving us a grand total of 1024KB(1MB) of storage capacity.

The idea of linking chips together to create memory banks, and thus, more storage has been used since the advent of computing, and still exists today. It's far cheaper for a manufacturer to fabricate lower density chips and arrange them in banks, than to create a single large capacity module. Doing such would present other obstacles to the performance and reliability of the device. Not only would the device itself be physically larger, but also it would also require more energy to power, and would probably be slower to access information from. The additional complexity would also, most likely, reduce the reliability of the device.

Paged RAM

Since the first PCs hit the market over ten years ago, Dynamic RAM has been the memory of choice for a majority of applications. DRAM has undergone quite a bit of renovation and by today's standards the memory of yesterday is a technological dinosaur. Today's memory runs much cooler, faster, and uses less energy.

You can think of memory paging as being the same as the layout of a book. Books contain a "table of contents" that allows a reader to see the main topics and on what pages they can find them. Readers also use a bookmark to keep track of where they are in a book. Memory paging works on the exact same concept. The memory itself is divided up into pages, and a table of contents is kept so that it knows what page is currently open, and what data and programs are stored where. Instead of having the system look up a single bit at a time, you would have it look up a "page" of memory, which reduced the cycle time of memory accesses and writes. If you needed to get information off another page, and don't know where it is, then you have to close the book, go back to the table of contents, then open to the new page. This equates to latency.

About the time that the first Pentiums were released on the market came the release of "Fast Page" RAM. This type of RAM functions exactly the same as the original Paged RAM, but it did it (surprise!) faster. Since RAM was becoming much more reliable, parity memory checking was removed, and the bus width of the memory was increased to match the processor's bus width as well as increases in clock speed. Unfortunately, improvements in memory speed didn't keep pace with the speed of the processors.