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Dual Coppermine 733 Hands-on Preview
November 22, 1999   James Yu > [View My Other Articles]
Product Info | User Reviews | Article Images(3) | Image Gallery | Comments | Forum Thread
What's New?

Aluminum-mine

Despite the Coppermine codename, the new P3 processors still use aluminum. Intel won't start using copper until 2001 when production shifts to the smaller 0.13 micron process. AMD has already announced that its first 0.18 Athlon chips will use aluminum interconnects, but will switch to copper.

Let's go over a few of the differences between the old Katmai Pentium 3 and the new Coppermine P3. First, the Coppermine uses a .18 manufacturing process while the Katmai uses a larger 0.25 process. The Coppermine also has 6 metal layers, one more than the Katmai's 5 layers.

The smaller process allows Intel to fit more processors on each wafer, while reducing power consumption. The 0.25 Katmai P3 processors require 2.00-2.05V, but the Coppermine P3 processors only need 1.1-1.7V. The Coppermine P3 also features over 28 million transistors, almost three times as many as the Katmai's 9.5 million. The smaller process also allows processors to run cooler and reach higher speeds.

L2 cache

Why does the Coppermine have almost three times as many transistors as the Katmai? Well, the on die L2 cache might have something to do with the transistor count increase. The Katmai design has 512KB of discrete L2 cache running at half the processor speed. You can find the L2 cache SRAM chips sitting to the right of the processor core on each Katmai CPU.

For the Coppermine, Intel engineers halved the size of the L2 cache to 256KB and moved it onto the processor core (on die). Now the Coppermine P3 processors have 256KB of L2 cache running at full processor clock speed. Moving the cache on die will allow Intel to abandon the slot based processor format and return completely to the cheaper socket format, because the processor no longer needs the extra space for the discrete SRAM chips. The L1 cache size remains the same at 32KB.

Advanced Transfer Cache

In addition to moving the L2 cache onto the core, Intel has also made a couple of other cache changes to increase performance. The 64-bit L2 cache data bus between the cache and the core has increased to 256-bits. Cache design has also been changed from 4-way set associative to 8-way set associative. Increasing the degree of associativity usually decreases the miss rate, but increases the hit time.

The new Coppermine technology also features "Advanced System Buffering." The Katmai only has four fill buffers, four bus queue entries, and one writeback buffer. The Coppermine has 6 fill buffers, 8 bus queue entries and 4 writeback buffers.

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The three main caching schemes are direct mapped, set associative, and fully associative. You can consult your nearest Patterson and Hennessy text for full definitions.


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