In November, 1995 Intel first introduced the world to its first P6 processor, the Pentium Pro. The Pentium Pro was Intelís first processor to boast support for speculative execution. This refers to the processor's ability to look at instructions ahead in the program and determine which instructions are dependent on each other. It then executed the instructions in the most efficient way possible while retiring them in the order they were originally written. Another feature of the Pentium Pro was its superpipelined architecture -- work was split into 12 stages, versus the five stages used in the original Pentium processor. This allowed the Pentium Pro processor to scale to higher clock speeds even though it was still based on the same 0.35-micron manufacturing process.
Why are we devoting so much time to the Pentium Pro in an article on Intelís latest Core 2 processor you ask? Because the Pentium Proís P6 microarchitecture eventually went on to become Intelís best-selling CPU, powering the guts behind the Pentium II and eventually the Pentium III, and in some ways you could definitely argue that some of the basic attributes found in todayís Core 2 CPUs dates back to the good Ďol P6 Pentium Pro. Before we elaborate further on that though letís briefly discuss Coreís predecessor, the Pentium 4/D
Core 2 (right) sits with Pentium 4
Core 2 and the Athlon 64 X2 5000+
It has been over five years since Intel first launched their Netburst microarchitecture used in the Pentium 4. Netburst was designed in part to solve the Pentium IIIís then biggest weakness, its inability to scale well beyond 1.2GHz. At the time the Pentium 4 debuted, the Pentium III was basically stuck right around 1.0GHz.
To solve this problem, Intel dramatically increased the number of pipeline stages in Pentium 4, going from 10 stages in the Pentium III to 20 stages in the original Pentium 4. By increasing the number of pipeline stages, Intel sacrificed the number of instructions that the CPU could execute per clock cycle (IPC) for higher clock speeds. Remember, as a general rule of thumb a CPUís performance comes from two key areas: instructions per clock cycle (IPC) and clock speed. The formula is:
Performance = IPC x Clock Speed
With its 20-stage pipeline, Intel's Pentium 4 microarchitecture sacrificed the amount of work performed per clock for more stages. The upside of the P4ís twenty stage pipeline was that it allowed the processor to scale to clock frequencies that were much higher than Pentium III when using the same manufacturing process. The downside was that the Pentium 4 was doing less work per MHz.
Quite simply, with Pentium 4 Intel designed the P4 to run at high clock speeds to make up for the lower amount of work performed per clock cycle, the "IPC" from the above formula. Sheer clock frequency would essentially make up for the lower IPC from the processor performance equation. Of course, what Intel didnít envision was what would happen when the Pentium 4 scaled to very high clock speeds. In order to keep processor yields high at faster clock speeds, they added 11 stages to their Prescott Pentium 4 CPU core (for a total of 31). At the time Prescott debuted in February, Intel was shooting to hit 4GHz by the end of the year. Ultimately though, as the Pentium 4ís clock speeds cranked up closer to 4GHz, power consumption became harder to keep in check, while the processor also began to generate an excessive amount of heat (this was partially due to increased gate leakage Intel encountered at 90-nm). A solution was needed and it was needed quickly.
Meanwhile, while all this was going on, Intelís mobile design team in Israel had just successfully developed Pentium M, internally codenamed by Intel as ďBaniasĒ. (Pentium M) Banias improved upon the P6 microarchitecture, topping out at lower clock speeds than the Pentium 4, but still delivering good performance while also drawing much less power. Follow-up parts improved performance even further by integrating larger caches, and earlier this year Intel improved Pentium M even further by cranking up the bus speed to 667MHz FSB and incorporating SSE3 instructions among other improvements. This CPU, codenamed Yonah, is the Core Duo CPU that have been embraced by Apple.
For their Core 2 family of CPUs, Intelís essentially taken the playbook used so successfully in the Core Duo and tweaked it into their latest next-generation CPU, previously codenamed ďConroeĒ. Up for review today are two of Intelís higher-end Conroe CPUs, the Core 2 Extreme X6800 and the Core 2 Duo E6700. Letís take a look at whatís new with these processors, and Core 2 in general.