Resurfacing the Streets

Bye Bye, FSB

Intel’s use of the front side bus has taken fire ever since AMD adopted the HyperTransport interface. Back then, single-core CPUs were still in vogue and the FSB wasn’t a liability. But now Intel is selling processors with four cores on a single package, and when data in one core is needed by another, it has to travel out over the FSB to the MCH and back onto the CPU.

As they say, the devil is in the details and you probably don’t care how information is moving in your system, so long as Crysis is running at a playable frame rate or your video decode is smooth. Intel wants to improve its communications situation there, though. And so the company is eradicating the traditional front-side bus in favor of the QuickPath Interconnect (formerly referred to as CSI). QPI is point-to-point, like HyperTransport. And while representatives at Intel stop one step short of calling it a serial link, since data still moves in parallel, the QPI is much narrower and much faster than the front-side bus of old. In fact, a QPI link runs at 6.4 Gigatransfers per second, delivering up to 25 GBps of bandwidth. Each Nehalem-based CPU features two QPI links, creating a triangle in a dual-chip server configuration between both processors and an I/O hub. You’ll only use one link on a 1P desktop.

Bear in mind this is a high-end desktop. Mainstream systems won't include Tylersburg

According to Jeff Casazza, technology marketing manager in Intel’s server platform group, QuickPath will make the biggest impact in the server world, where multi-core chips and multiple processor sockets resulted in the worst digital traffic jams.

Hello, Memory Controller

As the front-side bus fades to black, Intel will also introduce its first integrated memory controller, which Pat Gelsinger says supports DDR3 at 800, 1066, and 1333 MHz. The controller sports three channels per processor, pumping out copious bandwidth. Of course, that also means installing memory modules three at a time if you’re hoping to maximize performance. That’s six at a time if you’re building a server or workstation with two CPUs. Then again, in a 2P configuration, Intel says DDR3-1333 will deliver four times more memory bandwidth that today’s Harpertown architecture on a 1600 MHz FSB. Talk about opening the floodgates.

Obviously, this is a complete re-haul of Intel’s existing platform design where you have a processor connected to a memory controller hub, which is then joined up to an I/O controller hub. Instead, a high-end Nehalem-compatible chipset will look a lot more like AMD’s 790FX with one northbridge component dedicated to PCI Express connectivity and a southbridge responsible for storage, sound, USB, and so on.

As you move down to the mainstream level, the core logic story gets even simpler. The I/O controller hub that delivered PCI Express functionality disappears and the Nehalem processor hooks right up to the southbridge What was once a three-chip platform (CPU, northbridge, and southbridge) turns into a two-chip configuration. Hopefully, the arrangement helps reduce costs as entry-level Nehalem systems emerge in 2009.