LS-DYNA benchmarks

In the above cases, we saw superb scaling of the V8 core over quad core and dual core systems from Intel. The story was different as our benchmarks got more complex.



LS-DYNA is a general purpose transient finite-element solver. It’s used to simulate all sorts of things ranging from metal forming applications and structural analysis to large deformation studies like bird strike simulations in aerospace applications. It has its roots from Lawrence Livermore Laboratories as the solver used to simulate nuclear warhead design. It’s auto-parallelization is superb and this is a great real-world test of something other than “embarassingly parallel” computational science.

In this benchmark, I chose to perform a car crash simulation using a dataset available in the public domain. To make testing easier, I only simulated a single time step of a 535,000 element model of a Plymouth Neon crashing into a barrier.

There are a few interesting points to be drawn from the graph. There was a near linear increase in performance going from the 1.8GHz Core 2 Duo to the 3.0GHz Core 2 Duo. Going from two 3GHz cores to four 3GHz cores represented only a 66% improvement, and doubling the number of to eight cores only added another 35%.

Based upon data from Sun Microsystems, even AMD Opteron with Infiniband scales substantially better on the same benchmark. Going from one 3GHz Opteron to two single-core Opteron 3GHz’s improved performance 99%. Doubling that to four single-core Opteron 3GHz’s resulted in a 87% improvement. Doubling that to eight single-core Opteron 156’s resulted in a 93% improvement. Doubling that to sixteen single-core Opteron 156’s resulted in an 81% improvement...

In other words, for a memory-bandwidth intensive application such as LS-DYNA, going from dual core to octo core on the Intel platform meant improving productivity 2.25x. Going from two single-core Opterons to eight single-core Opterons with Infiniband interconnects improves productivity by 3.6x – this number should be even higher with native Hypertransport interconnects.