Joshua

The Specs

Socket 370
Celeron Compatible
P6 Bus
Integrated 64KB L1 Cache
Integrated Mutually Exclusive 256KB L2 Cache
133MHz Front Side Bus Support
3DNow!
Enhanced Dual Pipelined MMX and FPU
0.18 micron Manufacturing Process
22 Million Transistors PR 433, PR 466, PR 500, and PR 533 Speeds

Notes

The Cyrix III/Joshua is based on the "Cayenne" core, and will compete with Intel's Celeron processor. The Joshua was designed by VIA's Cyrix team in Richardson, Texas. The Joshua uses the same P6 bus and Socket 370 format as the Intel Celeron. Feature-wise, the Joshua has a couple notable advantages over the Celeron. The Joshua features 64KB of L1 cache and 256KB of integrated L2 cache. The Intel Celeron only features 32KB of L1 cache and 128KB of integrated L2 cache.

The Cyrix III also has 3DNow! support along with a dual pipelined MMX and floating point unit and a 133MHz front side bus. The Celeron won't gain SSE support until it moves over to the 0.18 micron Coppermine core. Even then, the Celeron will only feature 128KB of L2 cache and a 100MHz FSB, but clock speeds will be much higher.

The Cyrix III looks pretty good at first glance, but you also have to remember that AMD's K6-3 also features 3DNow!, and the same amount of cache. The Cyrix III seems to only have a single superpipelined integer unit, but we still have to confirm that cloudy point with VIA. The K6-2 and above have two integer units. The Cyrix III only features plain vanilla 3DNow!, not the Enhanced 3DNow! instructions available with the AMD Athlon.

The Cyrix III is not multiprocessor capable. According to Intel, the FC-PGA Pentium III processors are also uni-processor only, but we're sure Cyrix actually means it. The C3 is compatible with all Socket 370/Slot 1 north bridges and integrated chipsets including all VIA chipsets and Intel's 810, 810e, 820, BX, and others. Volume production will begin in April.