The most obvious disadvantage associated with an integrated memory controller is the risk of falling behind with regard to memory technology. Look at VIA’s product history, for example. VIA has traditionally made multiple revisions to its memory controllers in the name of milking extra performance from the Athlon XP and as a result we’ve seen KT133, KT133A, KT266, KT266A, etc.
AMD won’t have that luxury with the K8 family. Opteron currently supports dual-channel DDR333, while Intel is utilizing DDR400 on the recently introduced 875P chipset. So, if AMD hopes to remain competitive as Opteron evolves and Athlon 64 emerges, it will undoubtedly require more than one revised memory controller. After all, DDR-II isn’t that far over the horizon.
We were unfortunately unable to verify AMD’s claims of 10.6GB per second, as SiSoft Sandra 2003 was unable to properly identify the onboard memory controller and repeatedly returned a memory bandwidth figure around 500MB per second.
Formerly referred to as Lighting Data Transport, HyperTransport is AMD’s data transfer bus that facilitates interaction between the processor (or processors in a multi-processing environment), PCI-X Tunnels, I/O Hubs and AGP 8x Tunnels. The HT links within the Opteron are 16-bits wide for a resulting 3.2GB per second of unidirectional bandwidth. And, the Opteron has three such links whereas the Athlon 64 hosts a single link with 6.4GB per second of bidirectional bandwidth.
One of the main benefits of HyperTransport is its scalable nature. Running natively at 200MHz, HT can be pushed to 800MHz DDR, for n effective 1.6GHz. Furthermore, HyperTransport paths can be 2, 4, 8, 16, or 32-bits wide, offering anywhere from 200MB/s to 12.8GB/s of throughput. The effect AMD is looking for is an alleviation of front side bus, memory, chip-to-chip and I/O expansion bottlenecks.
The initial round of motherboards supporting the Opteron will be based on AMD’s own 8000-series chipset. As we’ve heard before, AMD is not a chipset manufacturer, so we’ll see what role it plays once the likes of SiS, AMD, and NVIDIA come online with their own products. Each component of AMD’s chipset connects to the HyperTransport bus through links with different throughputs. For instance, the 8111 I/O Hub features an 8-bit link with 800MB per second of aggregate bandwidth. The 8131 I/O Bus Tunnel is a higher-performance device with PCI-X support, necessitating more bandwidth. It connects via a 16-bit interface boasting 6.4GB per second. Similarly, the 8151 Graphics Tunnel utilizes one 16-bit connection.
AMD is quick to point out that, compared to Intel, it has successfully implemented 64-bit support without crippling the performance of 32-bit applications. The Opteron is backwards compatible with 32-bit code and the architectural extensions that have emerged over the past few years including MMX, 3DNow!, Enhanced 3DNow!, SSE and SSE2. Like the Athlon XP before it, Opteron sports 64KB of L1 data cache and 64KB of L1 instruction cache, in addition to a 1MB L2 cache that is 16-way set-associative. Finally, AMD has reportedly reduced the latencies of its Translational Lookaside Buffers (TLBs) and enhanced its branch predictor to help offset the ICP penalties potentially incurred by adding extra stages to the operation pipeline.