184 edge connector pads
Clock Frequency: 200 MHz
SSTL-2 interface: 2.5 Voltage +/- 0.2V


JEDEC Standard
A whopping 6.4GB/s of memory bandwidth
Date Rate:500MHz
Double Data Rate architecture
Bi-directional data strobe (DQS)
Different clock inputs (CK and /CK)
MRS cycle with address key programs
* CAS latency: CL2.5
* Burst length: 2, 4, 8
* Burst type: Sequential & Interleave

WLCSP package
*The smallest original chip dimension
*High stability of data transmission
*Good heat diffusion

2 variations of refresh
*Auto refresh & Self refresh

Edge aligned data output, center aligned data input
2 banks to be operated simultaneously or independently
Serial Presence Detect with EEPROM
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