Image: f 10
Backplate with indentions for cache chip
Jump to another image > a : Athlon's execution pipeline b : 3 pipelined FPU units c : Point-to-Point on 2 CPUs d : P2P vs. shared bus architecture e : The Athlon, head-on! f : Backplate with indentions for cache chip g : AMD-751 North Bridge w/o heatsink h : AMD-756 South Bridge i : Heatsinks over voltage regulators j : Winbond temperature management
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» RELATED FIRINGSQUAD ARTICLE Maintainer: Kenn Hwang Date: July 22, 1999 Category: Hardware : CPUs • Return to Article
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