Features

* 700 million transistors on 80nm HS fabrication process
* 512-bit 8-channel GDDR3/4 memory interface
* Ring Bus Memory Controller
o Fully distributed design with 1024-bit internal ring bus for memory reads and writes
o Optimized for high performance HDR (High Dynamic Range) rendering at high display resolutions
* Unified Superscalar Shader Architecture
o 320 stream processing units
+ Dynamic load balancing and resource allocation for vertex, geometry, and pixel shaders
+ Common instruction set and texture unit access supported for all types of shaders
+ Dedicated branch execution units and texture address processors
o 128-bit floating point precision for all operations
o Command processor for reduced CPU overhead
o Shader instruction and constant caches
o Up to 80 texture fetches per clock cycle
o Up to 128 textures per pixel
o Fully associative multi-level texture cache design
o DXTC and 3Dc+ texture compression
o High resolution texture support (up to 8192 x 8192)
o F.......

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